Liquid crystal display panel driving device

ABSTRACT

An analog driver for a liquid crystal display has sample hold circuits and buffer amplifiers divided into one group for positive inputs and the other groups for negative inputs which buffer amplifiers are selected in accordance with a first and second control signals thereby reducing the power consumption by the driver of buffer amplifiers. Furthermore, when none of the buffer amplifiers are selected, the data lines are held at common voltage to reduce the consumed power by the buffer amplifiers.

TECHNICAL FIELD

The present invention relates to a driver for a liquid crystal display(LCD), more panel particularly to an analog LCD driver for performing HVinversion or H inversion, and one or two sided drive.

BACKGROUND ART

Source drivers for driving a TFT (Thin Film Transistor)/LCD panel are ofdigital type and of analog type. According to the digital type,luminosity data corresponding to each pixel is delivered to a driver asa digital value and the driver latches the digital value and outputs thevoltage corresponding to it. Methods for outputting the voltage are aswitch scheme and a digital analog conversion (DAC) scheme. The switchscheme is performed by selecting and outputting one of a plurality ofreference voltages. A driver using this scheme, can employ 4 bits (16gradations) or 6 bits (64 gradations) requiring, but 16 or 64 switchesfor each output of the driver. It is impractical to implement gradationsof more than 6 bits. The DAC scheme is performed by preparing a DAC foreach output of the driver converting the received luminosity data intoan analog value output. Disadvantages of this scheme are that itrequires a large sized circuit and it is difficult to equate theperformance of DAC provided for each output.

The output voltage of such a digital driver normally ranges from 0 V to5 V. To cope with an LCD that is alternately driven between 0 V and 6 Vand between 0 V and −6 V, a scheme of common inversion drive is adopted.This common inversion drive, changes the voltage of the common electrodeof the LCD panel at a predetermined period (AC drive) as a result, theoutput of the driver appears to cover in the range of 1 V to 6 V andthat of −1 V to −6 V (the range of 1 V to −1 V is a non-sensitive band).The period for which the voltage of this common electrode can beAC-driven is limited to the period of a horizontal sync. signal (Hperiod). With this H inversion scheme, since a cross talk takes place inthe horizontal direction of the screen, the deterioration of the screenpresentation is inevitable.

With the analog type, conversion is not performed in each driver,luminosity data corresponding to each pixel is delivered to a driver inan analog value and the analog value is held in a sample hold circuitand outputted through a buffer amplifier. Since the analog type allowsvoltages of −6 V to 6 V can be outputted as a matter of course, it isunnecessary to perform the common inversion drive. While use of a highwithstand voltage element leads to an increase in the size of eachelement, with proper circuit design, there is a good possibility thatthe total size can be made smaller than that of the digital driver.Furthermore, because of being able to cope with an infinite levels ofgradations using the same circuit independently of the number ofgradations, the analog driver is fit to implement more 256 gradations(full color). In addition, since it is not required to perform a commoninversion drive, the HV inversion drive scheme which performsopposite-polarity write to neighboring pixels is implementable.Furthermore since no cross talk takes place, a high-quality image can bedisplayed.

While this, the analog type provides a high quality image, howeversignificant design effort is required to suppress the variation ofoutputs and the occurrence of errors to sufficiently low limits.Furthermore, an output amplifier with a large power consumption isneeded. As mentioned above, this is because outputs of from −6 V to 6 Vare needed.

Accordingly, analog drivers have thus far not been utilized often forpurposes having stringent requirements for power consumption, such asthe display of a notebook PC, where used most of them have beenlarge-sized drivers for high resolution displays, such as XGA or SVGA ina way to drive the source line of the LCD panel from the top and thebottom of the panel. In Published Unexamined Patent Application No.6-295162, a scheme of driving by the two-side drive method is described.

SUMMARY OF THE INVENTION

It is one object of the present invention, therefore, to provide an LCDpanel driver enabling the use of H inversion and HV inversion andenabling one and two-sided drive.

It is another object to reduce the power consumption in the analog LCDdriver.

To attain these objects, one aspect of LCD panel driver comprises: aplurality of sample hold and buffer amplification units for positiveinput each including a sample hold circuit for sampling and holding aninput video signal having a positive polarity in response to a firstcontrol signal (−SPP) and having a buffer amplifier activated during theholding for charging a data line in an LCD panel; a plurality of samplehold and buffer amplification units for negative input each including asample hold circuit for sampling and holding an input video signalhaving a negative polarity in response to a second control signal (+SPN)and having a buffer amplifier activated during the holding fordischarging a data line in an LCD panel; an output selector forselecting one of the buffer amplifiers in a group including one of theplurality of sample hold and buffer amplification units for a positiveinput and one of the plurality of sample hold and buffer amplificationunits for a negative input in response to a third control signal (B_SelP& N), wherein the output selector has means for connecting the data lineto a common voltage while no buffer amplifier is selected; abidirectional register for generating sampling pulses; and a controllerfor generating the first and second control signals which control thetiming of sampling and holding in the sample hold circuits and the thirdcontrol signal from a mode specification signal specifying whetherone-side drive or two-side drive, and HV inversion or H inversion, afourth control signal created in response to a Horizontal sync. signaland Vertical sync. signal to control the polarity of output voltage tothe LCD panel and the sampling pulses.

A user using this LCD panel driver inputs a mode specification signaldirecting whether one-side drive or two-side drive, and HV inversion orH inversion is performed. Using this mode specification signal and thefourth control signal created by the external controler from aHorizontal sync. (HS) signal and Vertical sync. (VS) signal, the thirdcontrol signal used in the output selector and the first and secondcontrol signal used in sample hold and buffer amplification units for apositive input and for a negative input are provided. In this manner, awide variety of user's requests can be accommodated.

In addition, the sample hold and buffer amplification units are dividedinto those for positive inputs and those for the negative inputs, andthose sample hold and buffer amplification units are selected by thefirst and second control signal. Therefore the drive of bufferamplifiers is cut in half. Futhermore, an output of the operating samplehold and buffer amplification unit selected by the third control signalis arranged so as to be outputted to the data line (source line) of theLCD panel during the period for which neither half of them is selected,the data line is connected to the common voltage. Accordingly the powerconsumption in the buffer amplifiers is reduced.

Another aspect of the present invention comprises: a plurality of samplehold and buffer amplification units for positive input each including asample hold circuit for sampling and holding an input video signalhaving a positive polarity in response to a first control signal (−SPP)and having a buffer amplifier activated during the holding for charginga data line in an LCD panel; a plurality of sample hold and bufferamplification units for negative input each including a sample holdcircuit for sampling and holding an input video signal having a negativepolarity in response to a second control signal (+SPN) and having abuffer amplifier activated during the holding for discharging a dataline in an LCD panel; an output selector for selecting one of the bufferamplifiers in a group including one of the plurality of sample hold andbuffer amplification units for a positive input and one of the pluralityof sample hold and buffer amplification units for a negative input inresponse to a third control signal (B_SelP & N), wherein the outputselector has means for connecting the data line to a common voltagewhile no buffer amplifier is selected; a bidirectional register forgenerating sampling pulses; a controller for generating the thirdcontrol signal and a fifth control signal for distributing the samplingpulses to any of the groups including the sample hold and bufferamplification units for a positive input and the sample hold and bufferamplification units for a negative input from a mode specificationsignal specifying whether one-side drive or two-side drive, and HVinversion or H inversion and a fourth control signal created in responseto a Horizontal sync. signal and Vertical sync. signal to control thepolarity of output voltage to the LCD panel; and a plurality of pulsedistributors for generating the first and second control signals whichcontrol the timing of sampling and holding in the sample hold circuitsfrom the fifth control signal and the sampling pulses.

With this aspect, the controller in the above-mentioned aspect isdivided into a controller and pulse distributors.

Furthermore, a still another aspect of the present invention comprises:a plurality of sample hold and buffer amplification units for positiveinput each including a sample hold circuit for sampling and holding aninput video signal having a positive polarity in response to a firstcontrol signal (−SPP) and having a buffer amplifier activated during theholding for charging a data line in an LCD panel; a plurality of samplehold and buffer amplification units for negative input each including asample hold circuit for sampling and holding an input video signalhaving a negative polarity in response to a second control signal (+SPN)and a buffer amplifier activated during the holding for discharging adata line in an LCD panel; an output selector for selecting one of thebuffer amplifiers in a group including one of the plurality of samplehold and buffer amplification units for a positive input and one of theplurality of sample hold and buffer amplification units for a negativeinput in response to a third control signal (B_SelP & N), wherein theoutput selector has means for connecting the data line to a commonvoltage while no buffer amplifier is selected; a bidirectional registerfor generating sampling pulses; and a controller for generating thethird control signal and a fourth control signal which controls thepolarity of the output to the LCD panel from a mode signal specifyingwhether one-side drive or two-side drive, and HV inversion or Hinversion and from a Horizontal sync. signal and Vertical sync. signaland a plurality of pulse distributors for generating the first andsecond control signals which control the timing of sampling and holdingin the sample hold circuits from the fourth control signal and thesampling pulses.

In this aspect, one section of the external controller is provided inthis driver. In other words, with the above two aspects, the fourthcontrol signal is created from the Horizontal sync. signal and Verticalsync. signal, while the section for creating this fourth control signalis also provided in the driver. In this manner, the configuration of anexternal controller is simplified.

In the above three aspects, it is advisable that each of the sample holdand buffer amplification units for a positive input and the sample holdand buffer amplification units for a negative input comprises: a firstswitching means having the input terminal for the input video signalwherein the first switching means is switched by a first switch signal;a second switching means having the input terminal connected to theoutput terminal of the first switching means wherein the secondswitching means is switched by the first switch signal; a hold capacitorhaving one terminal connected to the output terminal of the secondswitching logic for charging for the input video signal; a bufferamplifier whose input side is connected to the output terminal of thesecond switching means; and a third switching means having one terminalconnected to the input terminal of the second switching means and havingthe other terminal connected to the output side of the buffer amplifier,wherein the third switching means is switched by a second switch signal,wherein the first switch signal changes in such a manner as to activatethe first and second switch means for the sampling period and the secondswitch signal changes in such a manner as to activate the third switchmeans for the holding period. In such a sample hold and bufferamplification unit, a high-speed and accurate sample hold is performed.

Alternatively, the above hold capacitor may be connected to a means forcompensating a change in the hold voltage of the hold capacitor. In thismanner, a more accurate sample hold is performed.

It goes without saying that the above-mentioned LCD panel drivers areused in an LCD panel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the general outline of the presentinvention.

FIG. 2 is a block diagram showing a source driver 3 according to thepresent invention.

FIG. 3 is a schematic representation showing a case where H inversion isperformed with one-side drive.

FIG. 4 is a schematic representation showing a case where HV inversionis performed with one-side drive.

FIG. 5 is a schematic representation showing a case where H inversion isperformed with two-side drive.

FIG. 6 is a schematic representation showing a case where HV inversionis performed with two-side drive.

FIG. 7 is an operational illustration of a sequencer 1.

FIG. 8 is an operational illustration of a sequencer 2.

FIGS. 9A and 9B are waveform charts of signals related to the sequencers1 and 2.

FIG. 10 is an illustration of a pulse control and bias control circuit29.

FIG. 11 is a wave form chart of P_SelO_E and P_SelO_O for each mode.

FIGS. 12A and 12B illustrate a sampling pulse distributor 23.

FIG. 13 is a signal wave form showing the processing of the samplingpulse distributor 23.

FIG. 14 is an illustration of a sample hold circuit and buffer amplifier25.

FIG. 15 is a signal wave form showing the operation of the sample holdcircuit and buffer amplifier 25.

FIG. 16 is an illustration of a G short operation.

FIG. 17 is an illustration of one effect of a G short operation.

BEST MODE FOR CARRYING OUT THE INVENTION

The general outline of the present invention is shown in FIG. 1. An LCDpanel 1 comprises a number of cells corresponding to the number ofpixels, each composed of a transistor 105, liquid crystals (equivalentlycapacitance 107) and a common electrode 109. To the gate of thistransistor 105, a gate line 103 is connected and a source line 101 isconnected to the source of the gate. This common electrode 109 is set toa common voltage (on the order of 6.5 V).

A source driver 3 is connected to the source of the transistor 105provided for each cell of the LCD panel 1 and a gate driver 5 issimilarly connected to the gate of the transistor 105. The gate driver 5and source driver 3 are connected to an external controller 7, while thesource driver 3 is connected to a D/A converter 9.

The operation of this arrangement will be described. A digital videosignal read from a frame buffer (not shown) is converted into an analogvideo signal by the D/A converter 9. With an arrangement according tothe present invention, this analog signal is provided for each of RGB, apositive and negative signals for each are outputted through differentsignal lines and at that time a gamma compensation is preferablyperformed. The generated analog video signal is inputted to the sourcedriver 3. The controller 7 to which a Horizontal Sync. (HS) signal, aVertical Sync. (VS) signal or the like is inputted generates signalswhich control a signal output of the source driver 3 and source driver5. Thus, the source driver 3 outputs an analog video signal from the D/Aconverter 9 to an appropriate source line 101 at an appropriate timingand the gate driver 5 operates in such a manner as to activate anappropriate gate line 103 at an appropriate timing.

FIG. 2 shows the general outline of the source driver 3 related to thetarget of the present invention. As shown in FIG. 2. the source driver 3comprises a bidirectional shift driver 21, a sampling pulse distributer23, a sample hold circuit and buffer driver 25, an output selector 27and an inversion and bias control circuit 29. This one source driver isin charge of 240 pixels (80 pixels per color) therefore a panel having640×480 pixels per color, has 8 drivers driving the panel.

The bidirectional shift register 21 is a register for receiving a startpulse and shifting an output one by one synchronously with a clock, inother words, which turns the output SPO ON in response to receiving thefirst clock after the start pulse and turns ON the output SP1 at thenext clock. The reason why the operation must be bidirectional apossibility of shifting in two directions. This output SPn (n is forgeneralization) is set to a sampling pulse and by this sampling pulseand an output from the inversion and bias control circuit 29 describedlater, the source line 101 of the LCD panel 1 is driven at anappropriate timing with an appropriate polarity.

Now, the inversion and bias control circuit 29 for controlling theoperation of the source driver 3 will be described. To this inversionand bias control circuit 29, P_SelO, P_Sell, Mode 1, Mode 2 and GSMsignals are inputted. These P_SelO and P_Sell signals are generated byan external controller 7 (FIG. 1). The Mode 1 and Mode 2 signals are2-bit signals signifying whether there is to be one-side drive ortwo-side drive of the LCD panel or whether H inversion drive or HVinversion drive. For example, if the Mode 1 and Mode 2 signals bothindicate 0, they are generically referred to as Mode A and Mode A meansthat H inversion is performed at one-side drive (FIG. 3). Besides, ifthe Mode 1 signal indicates 0 and the Mode 2 signal indicates 1, it isgenerically referred to as Mode B and Mode B means that HV inversion isperformed at one-side drive (FIG. 4). Furthermore, in the case oftwo-side drive, a mode is specified for each of the source drivers 3provided at both sides. If the top side indicates the Mode A and thebottom side also indicates the Mode A, for example, it means that Hinversion is performed at two-side drive as shown in FIG. 5.Alternatively, if the top side is in the Mode A and the bottom side isin the generically-called Mode C having the Mode 1 signal indicating 1and the Mode 2 signal indicating 0, it means that HV inversion isperformed at two-side drive (FIG. 6). The GSM signal is a signal forselecting whether the technique described later of reducing the consumedpower of the source driver 3 is employed or not.

First, the way how to generate P_SelO and P_Sell signals generated in anexternal controller 7 will be described. These P_SelO and P_Sell signalsare generated by two sequencers following the state transitions shown inFIGS. 7 and 8. When the sequencer of FIG. 7 is reset, the state P_Selchanges into a state 00. In this state P_Sel, the first bit represents aP_SelO signal and the second bit represents a P_Sell signal. Then, ifthe Horizontal Sync. signal (HS) is asserted (becomes _HS) and the stateInit_P of the sequencer shown in FIG. 8 is not a state 011 (!=means ≢),the sequencer changes into a state 10. Thus, the P_SelO signal changesto 1. In the state 00, when the state Init_P is a state 011 and the HSis asserted, the state changes to 01. Thus, the P_Sell signal changesto 1. In the state 00, even if other changes than these two take place,no change from the state 00 occurs. In the state 10, no state changeoccurs while the HS is asserted, but the state changes to 11 after theassert of HS ends. Thus, the P_Sell signal also changes to 1. In thestate of 11, when the Init_P is a state 100 and the HS is againasserted, the state returns to 10. Thus, the P_Sell signal becomes 0.Alternatively, when the Init_P is not the state 100 and the HS is againasserted, the state changes to 01. Thus, the P_SelO changes to 0.Otherwise, the state remains 11. Furthermore if previously asserted HSreturns, the state 01 transits to state 00 thus P_Sell also changes to0. Otherwise, the state remains 01. In this manner, the P_SelO andP_Sell signals change.

Referring to FIG. 8 when the sequencer is reset, the state Init_Pchanges into a state 000 and remains this till the Vertical Sync. signal(VS) is asserted (becomes _VS). When the VS is asserted, the statechanges to 100 and remains the state 100 while the state P_Sel is thestate 00 or (designated with #) the state 11 (when the P_SelO signal is0 and the P_Sell signal is 0, or when the P_SelO signal is 1 and theP_Sell signal is 1). However, if the state P_Sel is 10 or 01 (when theP_SelO signal is 0 and the P_Sell signal is 1, or when the P_SelO signalis 1 and the P_Sell signal is 0), the state changes to 110. In thisstate 110, if the VS remains asserted, the state does not change, butwhen the assert of VS ends, the state changes to 111. In the state 111,no state change takes place while the VS is not asserted, but when theVS is again asserted, the state changes to 011. This state 011 undergoesthe same change as with the state 100. Thus, there is no state changewhile the state P_Sel is the state 00 or a state 11, but if the stateP_Sel is 10 or 01, the state changes to 001. In the state 001, there isno state change while the VS does not change, but when the assert of VSends, the state returns to 000.

If observed in wave forms of actual signals, these state changes are asshown in FIG. 9. This wave form chart shows the period of VS beingasserted twice in two columns. Reference to FIGS. 7 and 8 showing thestate transitions of the above-mentioned sequencers leads tounderstanding that the wave forms follow the above description andaccordingly a detailed description is omitted. However, there is a waveform in which the P_Sell alone changes to 1 after the second assertionof the VS in the second column and the assertion of the HS, this occursbecause a voltage of different polarity must be given to the same pixelone for each VS period regardless of whether H inversion or HVinversion. Incidentally, a normal operation of the above sequencersrequires a condition that the HS is asserted after the VS is asserted.

Thus far, signals inputted to the inversion and bias control circuit 29have been described, but next, the processing in the inversion and biascontrol circuit 29 is shown in FIG. 10. The input signals describedabove are inputted from the left and outputs are shown on the right.Since individual circuits are combinations of elements well known tothose skilled in the art, a detailed description is omitted but thecircuit denoted by 111 shows an analog switch. For example, it is acircuit comprising the combination of a P-channel FET and an N-channelFET and may comprise either of them.

The output signals will be described from the top. +Bias P_E, −Bias N_E,+Bias P_O and −Bias N_O are bias control signals as shown in FIG. 2 andare inputted to sample hold circuits and buffer amplifiers 25. The +BiasP_E and +Bias P_O are signals activating the buffer amplifier of asample hold and buffer amplification unit for a positive input asmentioned later. With respect to the difference between E and O,identification numerals (SO to S239) attached to the output selector 27connected to the relevant buffer amplifier indicate that +Bias P_E isinputted if they are even and indicate that +Bias P_O is inputted ifthey are odd. These signals are generated by the bias control sectionusing a current mirror. Similarly, the −Bias N_E and −Bias N_O aresignals activating the buffer amplifier of a sample hold and bufferamplification unit for a negative input.

Besides, P_SelO_O and P_SelO_E are pulse control signals in FIG. 2 andare inputted to a sampling pulse distributor 23. These signals aresignals for specifying the destination of distributing a sampling pulsegenerated by the bidirectional shift register 21. The difference betweenE and O is similar to the one described above and will be describedlater in detail. FIG. 11 shows signal wave forms of these signals duringeach mode.

The rest of signals are output control signals in FIG. 2 and areinputted to the output selector 27. The GShort signal is a signal forcontrolling the power-saving in a case where the power-saving mode isspecified by the GSM signal. And, −B_Sel_E_P, −B_Sel_O_P, +B_Sel_E_N and+B_Sel_O_N are used for the control of the output selection of theoutput selector 27. That is, when the −B_Sel_E_N and −B_Sel_O_N areactivated, an output from the buffer amplifier for a positive input areoutputted to the LCD panel. Alternatively, when +B_Sel_E_N and+B_Sel_O_N are activated, an output from the buffer amplifier for anegative input are outputted to the LCD panel. The difference between Eand O is similar to the one described above.

Heretofore, the input signals shown in FIG. 2 can be described as inputsignals to the sampling pulse distributor 23. Such being the case, next,description of the sampling pulse distributor 23 will be performed usingFIG. 12. Outputs from the bidirectional shift register 21 arerespectively distributed to three sections Dn. If n of this Dn is odd,the P_SelO_O described above is inputted to the section Dn.Alternatively, if n is even, the P_SelO_E is inputted to the section Dn.Each Dn generates two outputs, i.e., −SPP and +SPN. The suffixes ofthese −SPP and +SPN are the color in charge and serial number of theoutput destination. The constitution of each Dn is described in thedotted line, but uses elements well known to those skilled in the artare used and will not be further described. Incidentally, +P_SelO iseither P_SelO_O or P_SelO_E and −P_SelO is a signal having an oppositepolarity of +P_SelO.

If expressed in a wave form chart, such processing in the sampling pulse23 causes changes in the signals in FIG. 13. As shown in FIG. 11,P_SelO_E and P_SelO_O differ with the respective mode specifications,but when P_SelO_E or P_SelO_O forms a wave form as shown in (a) and asampling pulse from the bidirectional shift register 21 is such as shownin (b), the outputs become such as shown in (c) and (d). To be specific,if P_SelO_E or P_SelO_O is 1, +SPN is activated at the timing and forthe period of a sampling pulse. While P_SelO_E or P_SelO_O is 1, −SPP isinactivated. Or if P_SelO_E or P_SelO_O is 0, −SPP is activated at thetiming and for the period of the sampling pulse. While P_SelO_E orP_SelO_O is 0, +SPN is inactivated. Like this, with a change in P_SelO_Eor P_SelO_O, the period of +SPN and −SPP being active changes.

Next, FIG. 14 shows the configuration of sample hold circuits and bufferamplifiers 25 and the output selector 27. Sample hold circuits andbuffers amplifiers 25 can be divided into a sample hold circuit andbuffer amplification unit 41 for a positive input and a sample holdcircuit and buffer amplification unit 43 for a negative input. First,the sample hold circuit and buffer amplification unit 41 for a positiveinput comprises two P-channel FETs 51 and 53 with the gate connected to−SPP and a P-channel FET 55 with the gate connected to −B_SelP, all ofwhich are connected in the shape of T. To the output side of theP-channel FET 53, a hold capacitor 63 for holding the sampled voltage isconnected and further a buffer amplifier 59 is also connected. Thisbuffer amplifier 59 performs only the charging (injection of current).To the power source part of the buffer amplifier 59, an N-channel FET 57for bias is connected, to the gate of which +Bias P is connected.Furthermore, to the hold capacitor 63, a P-channel FET 61, which iscompensating circuit, is connected and compensates voltage held in thehold capacitor 63 due to the gate-source capacity of a switch forsampling at the moment of switching from ON to OFF of the switch forsampling by the voltage of +CMPP compensating signal.

On the other hand, the sample hold circuit and buffer amplification unit43 for a negative input comprises two N-channel FETs 65 and 67 with thegate connected to +SPN and an N-channel FET 69 with the gate connectedto +B_SelN, all of which are connected also in the shape of T. To theoutput side of the N-channel FET 67, a hold capacitor 77 for holding thesampled voltage is connected and further a buffer amplifier 73 is alsoconnected. This buffer amplifier 73 performs only the discharging(suction of current). To the power source part of the buffer amplifier73, a P-channel FET 71 for bias is connected, to the gate of which −BiasN is connected. Furthermore, the hold capacitor 77 is connected to acompensating circuit 75 which is controlled by −CMPN compensating signalas with the one for a positive input.

Next, the configuration of the output selector 27 will be described. Theoutput selector 27 comprises a P-channel FET 79 to the gate of which asignal −B_SelP, inputted to the gate of the FET 55, is also inputted, anN-channel FET 81 to the gate of which a signal +B_SelN, inputted to thegate of the FET 69, is also input, and an N-channel FET 83 for G shortto the gate of which a GShort signal is inputted.

First, since the configuration of the sample hold circuit is almostidentical for a positive input and for a negative input, the operationthereof will be briefly described using one for a positive input as anexample. The sample hold circuit generally has a period for sampling anda period for holding the sampled voltage. While activated by −SPP, theFETs 51 and 53 pass +Vin as an input signal, charges the hold capacitor63 and performs the sampling. The capacity of this hold capacitor 63affects the operating speed of this sample hold circuit. In other words,with a smaller capacity, the operation becomes speedier. For thisperiod, the FET 55 is turned OFF by −B_SelP. The sampling period (periodduring which the FETs 51 and 53 are turned ON) is only a period duringwhich an analog signal concerning the pixel in charge of this samplehold circuit and buffer amplifier 25 is inputted. And, when the samplingperiod ends and the hold period starts, the FET 55 is turned ON and theFETs 51 and 53 are turned OFF. Thereby, an input signal +Vin signalcomes not to arrive at the hold capacitor 63. Besides, since the FET 55is turned ON, an output of the buffer amplifier 59 comes to arrive atthe connection point of the FETs 51 and 53. Accordingly, the input andoutput of the buffer amplifier 59 and the connection point of the FETs51 and 53 become equal in potential and a noise from +Vin does notarrive at the output of the buffer amplifier 59. Thus, the voltageretained in the hold capacity 63 comes to be outputted accurately as itis. A more detailed content is described in Japanese Patent ApplicationNo. 6-322957.

Thereupon, referring to the wave forms of FIG. 15 base on this, theoperation of the arrangement of FIG. 14 will be described. On beingactivated, +SPN (f) generated by the sampling pulse distributor 23 makesthe negative video input −Vin of that time sampled. Thus, because thismeans the sampling period, −BiasN (h) is not turned ON and the bufferamplifier 73 does not operate. Besides, since +B_SelN (b) is also notactivated, the FET 69 is turned OFF and the FET 81 for output selectionis also turned OFF, so that the sample hold and buffer amplificationunit 43 for a negative input does not output. Incidentally, becausethere is no need for the compensation of the potential of the holdcapacitor 77 during the sampling period, −CMPN (g) is also notactivated. In contrast to this, the sample hold and buffer amplificationunit 41 for a positive input is during the hold period, −SPP (c) remainsOFF and −B_SelP (a) changes to ON. Thus, the FETs 51 and 53 remain OFFand the FET 79 for output selection is turned ON. Besides, since +BiasP(e) is activated, the buffer amplifier 59 becomes in operation and thevoltage retained in the hold capacitor 63 is outputted. The bufferamplifier 59 performs the discharging alone. Incidentally, a correctionsignal +CMPP (d) also turns ON and the correction of voltage is carriedout.

Here, −B_SelP (a) and +B_SelN (b) do not fall at the same time. As aresult, if the GSM signal described above is turned ON and thepower-saving mode is selected, GShort (i) becomes active during a lagbetween the falls of these signals and the FET 83 turns ON, so that thesource line is connected to a common voltage. This operation will bedescribed later. Accordingly, there is a period where an output of thebuffer amplifier neither for a positive input nor for a negative inputis selected, and the Vout line becomes a HiZ state for this period.Then, the voltage of the sourceline makes the common voltage by the FET83.

And this time, in such a manner as to sample a positive video input+Vin, −SPP (c) generated by the sampling pulse distributor 23 isactivated at the timing and for the period shown in the Figure. For thisduration, charge is stored in the hold capacitor 63. During thissampling period, +BiasP (e) is turned OFF and the buffer amplifier 59does not operate. In addition, since −B_SelP (a) is in the OFF state,the FETs 55 and 79 turn OFF and output is not selected. Incidentally,during the sampling period, because no compensation is needed, +CMPP (d)is not activated. This period corresponds to the hold period in thesample hold and buffer amplification unit 43 for a negative input. Thus,−BiasN (h) is activated to allow the buffer amplifier 73 to operate,output is selected with +B_SelN (b) and the voltage retained in the holdcapacity 77 is outputted to the source line (Vout) of the LCD panel. Atthis time, the buffer amplifier 73 performs the charging. Incidentally,to compensate the voltage of the hold capacitor 73, −CMPN (g) is turnedON.

By such repeating, the sample hold operation, the output selection andthe GShort operation in response to a GShort signal are carried out. Asmentioned above, this GShort operation is an operation to connect thesource line (Vout, referred to as data line alternatively) to the commonvoltage in a state where no buffer amplifier is selected. Why suchoperation would lead to power saving? This is because the Vout line isshortcircuited to Vcomm (voltage of the opposite electrode) by theGShort operation, thus eliminating the need for the drive portion ofthose buffer amplifiers, whereas formerly in the case of a change from−6 V (−Vcc) to +6 V (+Vcc) or in the case of a change from +6 V to −6 V,drive is performed entirely over the portion of 12 V, as shown in FIG.16. Thus, it is only necessary to drive by the portion of more thanVcomm if the drive of +direction is required or to drive by the portionof less than Vcomm if the drive of −direction is required. In thismanner, the consumed power becomes nearly half of the former one. Thiseffect can be obtained both in H inversion and in HV inversion. Stillmore, in the case of HV inversion, there is also an effect that chargesare locally cancelled on the LCD panel as shown in FIG. 17 and an effectthat the amount of charges entering or exiting the common electrodebecomes small. FIG. 17 shows the state that FET 83 performing the GShortoperation are ON.

According to the above-mentioned configuration, the configurationconforming to the drive scheme selected by a user to be easilyimplemented and power saving to be greatly achieved, but theabove-mentioned configuration is only one example and may be changed andmodified variously. That is, mechanism of an external controller 7 isprovided apart from this source driver 3, but may be provided inside thesource driver 3. In this manner, input signals are simplified butgenerally, since an LCD panel cannot be composed of the single sourcedriver 3, the redundancy of circuits takes place. Besides, the logiccircuit shown in FIG. 10 is implementable also in other configurations,which is well known to those skilled in the art. Furthermore, thesequencers shown in FIGS. 7 and 8 are also similar.

Industrial Applicability

As mentioned above, the present invention could provide an LCD paneldriver enabling H inversion or HV inversion, and one-side drive ortwo-side drive.

In addition, power consumption in the analog driver could be alsoreduced.

What is claimed is:
 1. An LCD panel driver, comprising: a firstplurality of sample hold and buffer amplification units for positiveinputs each including a sample hold circuit for sampling and holding aninput video signal having a positive polarity in response to a firstcontrol signal and having a first buffer amplifier activated during saidholding for charging a data line in an LCD panel; a second plurality ofsample hold and buffer amplification units for negative input eachincluding a sample hold circuit for sampling and holding an input videosignal having a negative polarity in response to a second control signaland having a buffer amplifies activated during said holding fordischarging a data line in the LCD panel; an output selector forselecting in response to a third control signal one or another of saidbuffer amplifies in a group including one of said first plurality ofsample hold and buffer amplification units for positive input and one ofsaid second plurality of sample hold and buffer amplification units fornegative inputs, said outputs selector having means for making said dataline a common voltage selected to reduce power consumption by the bufferamplifiers while neither buffer amplifier in the group is selected; abidirectional shift register for generating sampling pulses; and acontroller for generating said first and second control signals whichcontrol the timing of sampling and holding in said sample hold circuitsand said third control signal from a mode specification signalspecifying whether one-sided drive or two-sided drive, and HV inversionor H inversion are performed, a fourth control signal created inresponse to a Horizontal sync. signal and Vertical sync. signal tocontrol the polarity of output voltage to said LCD panel and saidsampling pulses.
 2. An LCD panel driver, comprising: a first pluralityof sample hold and buffer amplification units for positive inputs eachincluding a sample hold circuit for sampling and holding an input videosignal having a positive polarity in response to a first control signaland having a buffer amplifier activated during said holding for charginga data line in an LCD panel; a second plurality of sample hold andbuffer amplification units for negative inputs each including a samplehold circuit for sampling and holding an input video signal having anegative polarity in response to a second control signal and having abuffer amplifier activated during said holding for discharging a dataline in the LCD panel; an output selector for selecting in response to athird control signal one or another of said buffer amplifiers in a groupincluding one of said first plurality of sample hold and bufferamplification units for positive input and one of said second pluralityof sample hold and buffer amplification units for negative input, saidoutput selector having means for making said data line a common voltagechosen to reduce power consumption by the buffer amplifiers while nobuffer amplifier in the group is selected; a bidirectional shiftregister for generating sampling pulses; a controller for generatingsaid third control signal and a fifth control signal for distributingsaid sampling pulses to said sample hold and buffer amplification unitsfor positive input and said sample hold and buffer amplification unitsfor negative input from a mode specification signal specifying whetherone-sided drive or two-sided drive, and HV inversion or H inversion areto be performed and a fourth control signal created in response to aHorizontal sync. signal and Vertical sync. signal to control thepolarity of output voltage to said LCD panel; and a plurality of pulsedistributors for generating said first and second control signals whichcontrol the timing of sampling and holding in said sample hold circuitsfrom said fifth control signal and said sampling pulses.
 3. An LCD paneldriver, comprising: a first plurality of sample hold and bufferamplification units for positive inputs each including a sample holdcircuit for sampling and holding an input video signal having a positivepolarity in response to a first control signal and having a bufferamplifier activated during said holding for charging a data line in anLCD panel; a second plurality of sample hold and buffer amplificationunits for negative inputs each including a sample hold circuit forsampling and holding an input video signal having a negative polarity inresponse to a second control signal and having a buffer amplifieractivated during said holding for discharging a data line in the LCDpanel; an output selector for select in response to a third controlsignal one or another of said buffer amplifiers in a group including oneof said first plurality of sample hold and buffer amplification unitsfor positive input and one of said second plurality of sample hold andbuffer amplification units for negative input, said output selectorhaving means for making said data line a common voltage chosen to reducepower consumption by the buffer amplifiers while no buffer amplifier inthe group is selected; a bidirectional shift register for generatingsampling pulses; and a controller for generating said third controlsignal and a fourth control signal which controls the polarity of theoutput to said LCD panel from a mode signal specifying whether one-sideddrive or two-sided drive, and HV inversion or H inversion are to beperformed and from a Horizontal sync. signal and Vertical sync. signal;and a plurality of pulse distributors for generating said first andsecond control signals which control the timing of sampling and holdingin said sample hold circuits from said fourth control signal and saidsampling pulses.
 4. The LCD panel driver as set forth in claim 1,wherein each of said sample hold and buffer amplification units forpositive inputs and said sample hold and having buffer amplificationunits for negative inputs comprises: a first switching means having aninput terminal for said input video signal, said first switching meansbeing switched by a first switch signal; a second switching means havingan input terminal connected to an output terminal of said firstswitching means, said second switching means being switched by saidfirst switch signal; a hold capacitor having one terminal connected tothe output terminal of said second switching means for charging for saidinput video signal; a buffer amplifier unit whose input side isconnected to the output terminal of said second switching means; and athird switching means having one terminal connected to the inputterminal of said second switching means and having the other terminalconnected to an output terminal of said buffer amplifier unit, saidthird switching means being switched by a second switch signal, saidfirst switch signal changing in such a manner as to activate said firstand second switching means for sampling during the sampling period andsaid second switch signal changing in such a manner as to activate saidthird switching means for the holding period to provide during theholding period an isolation signal through the third switching meansfrom the output of the buffer amplifier to the second switching means.5. The LCD panel driver as set forth in claim 4, wherein said holdcapacitor is connected to a compensating means for a change in the holdvoltage of said hold capacitor.
 6. The LCD panel driver of claim 4,wherein said first, second and third switching means for positive inputsare P-channel devices and said first, second and third switching meansfor negative inputs are N-channel devices.
 7. The LCD panel driver ofclaim 4, wherein said output selector in the group includes a fourthswitch means for selecting the buffer sample and hold and bufferamplification units for positive input; and a fifth switch means forselecting the sample and hold and buffer amplification units for anegative input.
 8. The LCD panel driver of claim 7, wherein said meansfor making said data line a common voltage includes a switch meansresponsive to a shorting signal to short the output of both the fourthand fifth switch means to ground when neither buffer amplifier in thegroup is selected.
 9. A liquid crystal display comprising: an LCD panel;and an LCD panel driver, wherein said LCD panel driver comprises: afirst plurality of sample hold and buffer amplification units forpositive inputs each including a sample hold circuit for sampling andholding an input video signal having a positive polarity in response toa first control signal and having a buffer amplifier activated duringsaid holding for charging a data line in the LCD panel; a secondplurality of sample hold and buffer amplification units for negativeinputs each including a sample hold circuit for sampling and holding aninput video signal having a negative polarity in response to a secondcontrol signal and having a buffer amplifier activated during saidholding for discharging a data line in the LCD panel; an output selectorfor selecting in response to a third control signal one of said bufferamplifiers in a group including one of said plurality of sample hold andbuffer amplification units for positive input and one of said pluralityof sample hold and buffer amplification units for negative input, saidoutput selector having means for making said data line a common voltageselected to reduce power consumption of the buffer amplifiers while nobuffer amplifier is selected; a bidirectional shift register forgenerating sampling pulses; and a controller for generating, said firstand second control signals which control the timing of sampling andholding in said sample and hold circuits and said third control signalfrom a mode specification signal specifying whether one-sided drive ortwo-sided drive, and HV inversion or H inversion are to be performed, afourth control signal created in response to a Horizontal sync. signaland Vertical sync. signal to control the polarity of output voltage tosaid LCD panel and said sampling pulses.
 10. The liquid crystal displayof claim 9 wherein said controller is for generating said third controlsignal and a fifth control signal for distributing said sampling pulsesto any of said groups including said sample hold and bufferamplification units for positive input and said sample hold and bufferamplification units for negative input from the mode specificationsignal specifying whether one-sided drive or two-sided drive, and HVinversion or H inversion are to be performed and a fourth control signalcreated in response to a Horizontal sync. signal and Vertical sync.signal to control the polarity of output voltage to said LCD panel; anda plurality of pulse distributors for generating said first and secondcontrol signals which control the timing of sampling and holding in saidsample hold circuits from said fifth control signal and said samplingpulses.
 11. The liquid crystal display of claim 9 wherein saidcontroller is also for generating said third control signal and a fourthcontrol signal which control the polarity of the output to said LCDdisplay panel from the mode signal specifying whether one-sided drive ortwo-sided drive, and HV inversion or H inversion are to be performed andfrom a Horizontal sync. signal and Vertical sync. signal; and aplurality of pulse distributors for generating said first and secondcontrol signals which control the timing of sampling and holding in saidsample hold circuits from said fourth control signal and said samplingpulses.
 12. The LCD panel driver as set forth in claim 9, wherein eachof said sample hold and buffer amplification units for positive inputsand said sample hold and having buffer amplification units for negativeinput comprises: a first switching means having an input terminal forsaid input video signal, said first switching means being switched by afirst switch signal; a second switching means having an input terminalconnected to an output terminal of said first switching means, saidsecond switching means being switched by said first switch signal; ahold capacitor having one terminal connected to the output terminal ofsaid second switching means for charging for said input video signal; abuffer amplifier unit whose input side is connected to the outputterminal of said second switching means; and a third switching meanshaving one terminal connected to the input terminal of said secondswitching means and having the other terminal connected to an outputterminal of said buffer amplifier unit, said third switching means beingswitched by a second switch signal, said first switch signal changing insuch a manner as to activate said first and second switching means forsampling during the sampling period and said second switch signalchanging in such a manner as to activate said third switching means forthe holding period to provide an isolation signal from the output of thebuffer amplifier to the second switching means during the holdingperiod.
 13. The LCD panel driver as set forth in claim 12, wherein saidhold capacitor is connected to a compensating means for a change in thehold voltage of said hold capacitor.
 14. The LCD panel driver of claim12, wherein said first, second and third switching means for positiveinputs are P-channel devices and said first, second and third switchingmeans for negative inputs are N-channel devices.
 15. The LCD paneldriver of claim 12, wherein said output selector in the group includes afourth switch means for selecting the buffer sample and hold and bufferamplification units for positive input; and a fifth switch means forselecting the sample and hold and buffer amplification units for anegative input.
 16. The LCD panel driver of claim 15, wherein said meansfor making said data line a common voltage includes a switch meansresponsive to a shorting signal to short the output of both the fourthand fifth switch means to ground when neither buffer amplifier in thegroup is selected.